This invention relates to a Schmitt trigger circuit (hysteresis circuit) using metal oxide semiconductor field effect transistors (MOSFETs).
Various types of Schmitt trigger circuits using MOSFETs are known. FIGS. 1 and 2 show typical examples of prior art Schmitt trigger circuits using complementary MOSFETs.
The prior art circuit shown in FIG. 1 is disclosed in an early published Japanese Patent Specification No. 54-121051, laid open on Sept. 19, 1979. This circuit comprises an input CMOS inverter 11 consisting of p-type transistors P.sub.1 and P.sub.2 and n-type transistors N.sub.1 and N.sub.2 ; a CMOS inverter 12 consisting of complementary transistors P.sub.4 and N.sub.4 connected to the output of the inverter 11; and additional transistors P.sub.3 and N.sub.3 which are connected respectively in parallel to the complementary transistors P.sub.1 and N.sub.1 and which are controlled by the inverter 12.
When an input voltage V.sub.in rises from zero volts and when it drops from V.sub.DD volts, the corresponding resistance ratios of the input CMOS inverter 11 are varied by the additional transistors P.sub.3 and N.sub.3 in response to an output voltage V.sub.out of the CMOS inverter 12, thereby realizing the hysteresis characteristic.
The operation of the circuit of FIG. 1 will now be described. It is assumed that threshold voltages of p-FETs and n-FETs are respectively V.sub.TP and V.sub.TN, ON resistances of p-FETs P.sub.1, P.sub.2 and P.sub.3 are respectively R.sub.P1, R.sub.P2 and R.sub.P3, and ON resistances of n-FETs N.sub.1, N.sub.2 and N.sub.3 are respectively R.sub.N1, R.sub.N2 and R.sub.N3.
When an input signal V.sub.in is at V.sub.DD volts (e.g. 5 volts), p-FETs P.sub.1 and P.sub.2 in the inverter 11 are nonconducting, while n-FETs N.sub.1 and N.sub.2 are conducting. Therefore, the output voltage V.sub.A of the inverter 11 is zero volts and the output voltage V.sub.out of the inverter 12 is V.sub.DD volts. Thus, FETs P.sub.3 and N.sub.3 are non-conducting and conducting, respectively.
When the input voltage V.sub.in drops from V.sub.DD -.vertline.V.sub.TP .vertline., p-FETs P.sub.1 and P.sub.2 are turned on, so that the output voltage V.sub.A of the inverter 11 will be ##EQU1## The output voltage V.sub.out is kept to V.sub.DD until V.sub.A reaches the threshold voltage V.sub.F of the inverter 12.
The ON resistance of each FET varies with the input voltage V.sub.in, and when V.sub.A exceeds V.sub.F, the output voltage V.sub.out of the inverter 12 is inverted from V.sub.DD to zero volts. The input voltage to invert the output voltage V.sub.out from V.sub.DD to zero volts is a lower threshold voltage V.sub.thL of the hysteresis circuit. When the input voltage V.sub.in is zero volts, p-FETs P.sub.1 and P.sub.2 are conducting, while n-FETs N.sub.1 and N.sub.2 are nonconducting. Thus, V.sub.A is V.sub.DD volts and V.sub.out is zero volts. At this time, p-FETs P.sub.3 and n-FET N.sub.3 are conducting and nonconducting, respectively.
In a case where the input voltage V.sub.in rises from zero volts, when V.sub.in exceeds the threshold voltage V.sub.TN of n-FETs N.sub.1 and N.sub.2, FETs N.sub.1 and N.sub.2 will turn on. At this time, V.sub.A is given by ##EQU2## V.sub.A drops with an increase in V.sub.in and when it falls below V.sub.F, the inverter 12 inverts the output voltage V.sub.out from zero volts to V.sub.DD volts. The input voltage to invert the output voltage V.sub.out from zero volts to V.sub.DD volts is a higher threshold voltage V.sub.thH of the hysteresis circuit. Suitable selection of the channel width and channel length of each of the MOS transistors which constitute the inverter 11, namely, the proper selection of the mutual conductance g.sub.m of each MOS transistor enables a modification of the hysteresis characteristic (threshold voltages and hysteresis width) of the hysteresis circuit.
With such a prior art hysteresis circuit, low-voltage and high-speed operation of the circuit are difficult since the CMOS inverter 11 at the input stage includes a series connection of four FETs P.sub.1, P.sub.2, N.sub.1 and N.sub.2 across the power supply. In addition, the threshold voltages of the circuit depend upon the ON resistances of FETs P.sub.1, P.sub.2, N.sub.1 and N.sub.2 when a current flows through the CMOS inverter 11 from the V.sub.DD terminal to the ground terminal. Therefore, the threshold voltages of the circuit are easily subject to change due to variations in the production processes.
FIG. 2 shows a Schmitt trigger circuit which is disclosed in an early published Japanese Patent Specification No. 57-67319, laid open Apr. 23, 1982.
For ease of explanation, in this circuit, the same elements as those shown in the circuit of FIG. 1 are designated by the same reference numerals. In this circuit, p-FET P.sub.3 is connected between a connection point 14 of p-FETs P.sub.1 and P.sub.2 and ground. On the other hand, n-FET N.sub.3 is connected between the V.sub.DD terminal and a connection point 15 of n-FETs N.sub.1 and N.sub.2. A CMOS inverter 13 is connected to the CMOS inverter 12, and complementary FETs P.sub.3 and N.sub.3 are controlled by the inverter 13.
In the operation of this circuit, when V.sub.in =0, p-FETs P.sub.1 and P.sub.2 are conducting and n-FETs N.sub.1 and N.sub.2 are nonconducting. Thus, V.sub.out is V.sub.DD and FETs P.sub.3 and N.sub.3 are nonconducting and conducting, respectively. Therefore, the circuit point 15 is raised to V.sub.DD -V.sub.TN. When V.sub.in rises from zero volts and exceeds V.sub.TN, n-FETs N.sub.1 and N.sub.2 conduct. At this time, the circuit point 15 is at V.sub.DD -V.sub.TN, so that the output voltage V.sub.A of the inverter 11 keeps V.sub.DD. Hence, the inverters 12 and 13 do not invert the output voltage V.sub.out.
When V.sub.in further increases and reaches, for example, 4 volts, the ON resistance of FET N.sub.1 becomes minimal and the voltage at the circuit point 15 is substantially at the ground level so that V.sub.A also approaches the ground level. Therefore, the inverters 12 and 13 invert V.sub.out from V.sub.DD to zero volts.
When V.sub.in =V.sub.DD, V.sub.out is zero volts, so that FET P.sub.3 is conducting. The voltage at the circuit point 14 is therefore lowered to .vertline.V.sub.TP .vertline.. Next, when V.sub.in drops from V.sub.DD and reaches V.sub.DD -.vertline.V.sub.TP .vertline., p-FETs P.sub.1 and P.sub.2 are turned on. However, since the circuit point 14 is at .vertline.V.sub.TP .vertline. due to conducting FET P.sub.3, V.sub.A is kept to zero volts. Therefore, the inverters 12 and 13 do not invert V.sub.out. When V.sub.in further drops and reaches, for example, 1 volt, the ON resistance of p-FET P.sub.1 becomes minimal, so that V.sub.A increases to V.sub.DD. Hence, the inverters 12 and 13 invert V.sub.out from zero volts to V.sub.DD volts.
With a Schmitt trigger circuit as shown in FIG. 2, low-voltage operation and high-speed operation are difficult like the circuit shown in FIG. 1 since a series connection of four FETs is used. However, one of the threshold voltages of the circuit depends upon the ratio of the ON resistances of p-FETs P.sub.1 and P.sub.3, and the other threshold voltage depends upon the ratio of the ON resistances of n-FETs N.sub.1 and N.sub.2, namely upon the ratio of the ON resistances of FETs of the same channel type; therefore, the change of threshold voltages of the circuit due to variations in the production processes is less than the circuit shown in FIG. 1.